TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 18

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14. Serial Bus Interface (I2C/SIO)
x
13.4 Overview of SSP.................................................................................................................435
13.5 SSP operation......................................................................................................................439
13.6 Frame Format......................................................................................................................440
14.1 Configuration.......................................................................................................................448
14.2 Register................................................................................................................................449
14.3 I2C Bus Mode Data Format................................................................................................450
14.4 Control Registers in the I2C Bus Mode..............................................................................451
14.5 Control in the I2C Bus Mode..............................................................................................458
14.6 Data Transfer Procedure in the I2C Bus ModeI2C............................................................465
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10
13.3.11
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.5.1
13.5.2
13.5.3
13.6.1
13.6.2
13.6.3
14.2.1
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
14.5.9
14.5.10
14.5.11
14.5.12
14.5.13
14.5.14
14.5.15
14.5.16
14.6.1
14.6.2
14.5.1.1
14.5.1.2
Register List...................................................................................................................................................................425
SSPCR0(Control register 0)..........................................................................................................................................426
SSPCR1(Control register1)...........................................................................................................................................427
SSPDR(Data register)....................................................................................................................................................428
SSPSR(Status register)..................................................................................................................................................429
SSPCPSR (Clock prescale register)..............................................................................................................................430
SSPIMSC (Interrupt enable/disable register)................................................................................................................431
SSPRIS (Pre-enable interrupt status register)...............................................................................................................432
SSPMIS (Post-enable interrupt status register)............................................................................................................433
Clock prescaler..............................................................................................................................................................435
Transmit FIFO...............................................................................................................................................................435
Receive FIFO.................................................................................................................................................................435
Interrupt generation logic..............................................................................................................................................436
DMA interface...............................................................................................................................................................438
Initial setting for SSP....................................................................................................................................................439
Enabling SSP.................................................................................................................................................................439
Clock ratios....................................................................................................................................................................439
SSI frame format...........................................................................................................................................................441
SPI frame format...........................................................................................................................................................442
Microwire frame format................................................................................................................................................444
Registers for each channel............................................................................................................................................449
SBIxCR0(Control register 0)........................................................................................................................................451
SBIxCR1(Control register 1)........................................................................................................................................452
SBIxCR2(Control register 2)........................................................................................................................................454
SBIxSR (Status Register)..............................................................................................................................................455
SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................456
SBIxDBR (Serial bus interface data buffer register)....................................................................................................456
SBIxI2CAR (I2Cbus address register)..........................................................................................................................457
Serial Clock...................................................................................................................................................................458
Setting the Acknowledgement Mode............................................................................................................................459
Setting the Number of Bits per Transfer......................................................................................................................459
Slave Addressing and Address Recognition Mode......................................................................................................459
Operating mode.............................................................................................................................................................459
Configuring the SBI as a Transmitter or a Receiver....................................................................................................460
Configuring the SBI as a Master or a Slave.................................................................................................................460
Generating Start and Stop Conditions..........................................................................................................................460
Interrupt Service Request and Release.........................................................................................................................461
Device Initialization......................................................................................................................................................465
Generating the Start Condition and a Slave Address...................................................................................................465
SSPICR (Interrupt clear register)................................................................................................................................434
SSPDMACR (DMA control register).........................................................................................................................434
Arbitration Lost Detection Monitor............................................................................................................................461
Slave Address Match Detection Monitor....................................................................................................................463
General-call Detection Monitor...................................................................................................................................463
Last Received Bit Monitor..........................................................................................................................................463
Data Buffer Register (SBIxDBR)...............................................................................................................................463
Baud Rate Register (SBIxBR0)..................................................................................................................................464
Software Reset.............................................................................................................................................................464
Clock source
Clock Synchronization