TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 15

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

10. Static Memory Controller
11. 16-bit Timer / Event Counters (TMRB)
9.3 Block diagram.......................................................................................................................277
9.4 Description of Registers........................................................................................................278
9.5 Special Functions...................................................................................................................298
10.1 Function Overview..............................................................................................................301
10.2 Block diagram.....................................................................................................................301
10.3 Description of Registers......................................................................................................303
10.4 External Bus Cycle .............................................................................................................317
10.5 Connection example for external memory..........................................................................324
11.1 Outline.................................................................................................................................327
11.2 Differences in the Specifications........................................................................................328
11.3 Configuration.......................................................................................................................330
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10
9.4.11
9.4.12
9.4.13
9.4.14
9.4.15
9.4.16
9.4.17
9.5.1
9.5.2
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
10.3.10
10.3.11
10.3.12
10.3.13
10.3.14
10.4.1
10.4.2
10.4.1.1
10.4.1.2
10.4.1.3
10.4.1.4
10.4.2.1
10.4.2.2
10.4.2.3
DMAC register list..........................................................................................................................................................278
DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................279
DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................280
DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................281
DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................282
DMACIntErrClr (DMAC Interrupt Error Clear Register).............................................................................................283
DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)......................................................284
DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)....................................................................285
DMACEnbldChns (DMAC Enabled Channel Register)................................................................................................286
Scatter/gather function.....................................................................................................................................................298
Linked list operation........................................................................................................................................................299
DMACSoftBReq (DMAC Software Burst Request Register).....................................................................................287
DMACSoftSReq (DMAC Software Single Request Register)....................................................................................289
DMACConfiguration (DMAC Configuration Register)...............................................................................................290
DMACCxSrcAddr (DMAC Channelx Source Address Register)...............................................................................291
DMACCxDestAddr (DMAC Channelx Destination Address Register)......................................................................292
DMACCxLLI (DMAC Channelx Linked List Item Register).....................................................................................293
DMACCxControl (DMAC Channelx Control Register)..............................................................................................294
DMACCxConfiguration (DMAC Channelx Configuration Register)..........................................................................296
SFR List.........................................................................................................................................................................303
SMCMDMODE (Mode Register).................................................................................................................................304
smc_memif_cfg (SMC Memory Interface Configuration Register)............................................................................305
smc_direct_cmd (SMC Direct Command Register).....................................................................................................306
smc_set_cycles (SMC Set Cycles Register).................................................................................................................307
smc_set_opmode (SMC Set Opmode Register)...........................................................................................................308
smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 <0>).....................................................................................309
smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 <1>).....................................................................................310
smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 <2>).....................................................................................311
Separate bus mode.........................................................................................................................................................317
Multiplex mode..............................................................................................................................................................321
smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 <3>)...................................................................................312
smc_opmode0_0 (SMC Opmode Registers 0<0>).....................................................................................................313
smc_opmode0_1 (SMC Opmode Registers 0<1>).....................................................................................................314
smc_opmode0_2 (SMC Opmode Registers 0<2>).....................................................................................................315
smc_opmode0_3 (SMC Opmode Registers 0<3>).....................................................................................................316
tRC / tCEOE setting example
tWC / tWP setting example
tRC / tCEOE / tPC setting example
tTR setting example
tRC / tCEOE setting example
tWC / tWP setting example
tTR setting example
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