TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 425

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.12
SIOCLK
TXDCLK
12.12.1
12.12.2
12.12.2.1
12.12.2.2
Transmission
The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive counter.
In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse.
ted to the TXD pin on the falling edge of the shift clock outputted from the SCLK pin.
ted to the TXD pin on the rising or falling edge of the SCLK input signal according to the
SCxCR<SCLKS> setting.
edge of the next TXDCLK and the transmit shift clock signal is also generated.
15 16
Transmission Counter
Transmission Control
In the SCLK output mode with SCxCR<IOC> set to "0", each bit of data in the transmit buffer is output-
In the SCLK input mode with SCxCR<IOC> set to "1", each bit of data in the transmit buffer is output-
When the transmit data is written in the transmit buffer, data transmission is initiated on the rising
Figure 12-6 Generation of Transmission Clock in UART Mode
I/O interface Mode
UART Mode
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