TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 197

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

8.2.9
Type
8.2.9.1
8.2.9.2
in units of bits. Besides the general-purpose port function, the port I performs the functions of the External sig-
nal interrupt, CEC input function and the operation mode setting.
nal, if PI0 is "1", the device enters single chip mode and boots from the on-chip flash memory. If PI0 is "0",
the device enters single boot mode and boots from the internal boot program. For details of single boot
mode, refer to "Flash Memory Operation".
put in the PIIE register. These settings enable the interrupt input even if the CGSTBYCR<DRVE> bit in the
clock / mode control block is set to stop driving of pins during STOP mode.
Port I data register
Port I output control register
Port I function register 1
Port I open drain control register
Port I pull-up control register
Port I input control register
Port I (PI0 to PI3)
The port I is a general-purpose, 4-bit input/output port. For this port, inputs and outputs can be specified
While a reset signal is in "0" state, the PI0 input and pull-up are enabled. At the rising edge of the reset sig-
Reset initializes all bits of the port I as general-purpose ports with input and output disabled.
Pull-up is enabled for PI2, PI3 independently PIPUP register setting,
PI1 is N-ch open-drain ports independently PIOD register setting.
To use the external interrupt input for releasing STOP mode, select this function in the PIFR1 and enable in-
Note:In modes other than STOP mode, interrupt input is enabled regardless of the PIFR1 register setting
Port I Circuit Type
Port I register
if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device.
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7
6
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Register name
5
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Page 173
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4
PIDATA
PIPUP
PIFR1
PICR
PIOD
PIIE
T16
3
T16
Base Address = 0x400C_0800
2
Address (Base+)
0x002C
0x0000
0x0004
0x0008
0x0028
0x0038
T15
1
TMPM362F10FG
T14
0