TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 717

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TMPM362F10FG

Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet

Specifications of TMPM362F10FG

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
 Details
Other names
Q5704184A

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
Part Number:
TMPM362F10FG(C)
Manufacturer:
Toshiba
Quantity:
10 000
25.6.2
25.6.2.1
SMCCLK
A1 to A23 Valid → D0 to D15 Input
(Separate bus mode)
A1 to A23 Valid → D0 to D15 Input
(Multiplex bus mode)
A1 to A23 Valid → D0 to D15 Input
(Page access)
OE falling edge → D0 to D15 Input
OE Low-level pulse width
A1 ~ A23 Valid → OE falling edge
(Separate bus mode)
A1 ~ A16 Valid →OE falling edge
(Multiplex bus mode)
OE rising edge → D0 to D15 Hold
A1 to A23 Valid → D0 to D15 Hold
OE High-level pulse width
ALE Low-level pulse width
A1 to A16 Valid → ALE rising edge
ALE rising edge → A1to A16 Hold
OE rising edge → ALE falling edge
OE rising edge → A1to A16 Hold
OE rising edge → A1to A16 Output
"T" is 1/2 cycles of an internal bus frequency (fsys) in the Equation of the table.
AC measurement condition
Static memory controller (SMC)
・ Output levels : High = 0.7 x DVDD3, Low = 0.3 x DVDD3
・ Input levels : High = 0.7 x DVDD3, Low = 0.3 x DVDD3
・ Load capacity : CL = 40pF
Note:" Equation Measurement condition:
Basic Bus cycle (Read)
Parameter
N
K
P
=
=
=
t
t
t
WC
RC
TR
Cycle
Cycle
Cycle
Symbol
t
t
t
t
OEHW
t
t
t
AOEH
t
t
t
t
t
AOEL
OEW
CYC
ADH
OED
t
t
CAR
RAE
ADL
AD1
t
t
t
CLR
HR
HA
AL
LA
LL
≥ 3
≥ 3
≥ 1
(N − M)T − 13.0
, M
,
,
Page 693
(M)T − 15.0
(M)T − 15.0
(M)T − 13.0
(P)T − 13.0
(P)T − 13.0
(P)T − 13.0
Q
T − 13.0
T − 15.0
T − 10.0
L
31.25
0.00
0.00
Min
=
=
=
t
Equation
CEOE
t
t
WP
PC
Cycle
Cycle
Cycle
(N − M)T − 25.0
(N)T − 35.0
(N)T − 35.0
(Q)T − 35.0
2000
Max
≥ 1
≥ 1
≥ 1
fsys = 64 MHz
T=31.25
M = 1
Q = 2
N = 4
K = 5
L = 2
P = 2
31.3
90.0
90.0
27.5
68.8
80.8
16.3
16.3
0.00
0.00
18.3
18.3
16.3
21.3
49.5
49.5
49.5
TMPM362F10FG
Unit
ns

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