TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 490

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.6
Data Transfer Procedure in the I2C Bus ModeI2C
SCLx pin
SDAx pin
<PIN>
INTSBIx
Interrupt request
14.6.2.2
Settings in main routine
Reg.
Reg.
if Reg.
Then
SBIxCR1
SBIxCR1
SBIxCR2
tion bit from the master device during the first eight clocks on the SCL line.
address, the SBI pulls the SDA line to the "Low" level during the ninth clock and outputs an acknowledg-
ment signal.
"0". In the slave mode, the SBI holds the SCL line at the "Low" level while <PIN> is "0".
Figure 14-9 Generation of the Start Condition and a Slave Address
In the slave mode, the SBI receives the start condition and a slave address.
After receiving the start condition from the master device, the SBI receives a slave address and a direc-
If the received address matches its slave address specified at SBIxI2CAR or is equal to the general-call
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN> is cleared to
Slave mode
←
←
←
Example of INTSBI0 interrupt routine
←
←
≠
Start condition
7
SBIxSR
Reg. e 0x20
0x00
X
X
1
Clears the interrupt request.
Processing
End of interrupt
A6
6
X
X
1
1
5
X
X
1
A5
2
4
1
X
1
3
0
X
1
A4
3
2
X
X
0
Slave address + Direction bit
1
X
X
0
Page 466
A3
4
0
X
X
0
A2
5
Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
A1
6
A0
7
R/W
8
ACK
9
TMPM362F10FG
Master output
Slave output
Acknowledgement from
slave device