EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 155
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
July 2005
EP1S10
EP1S20
Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2)
Device
484-pin FineLine BGA Transmitter
672-pin FineLine BGA
672-pin BGA
780-pin FineLine BGA Transmitter
484-pin FineLine BGA Transmitter
672-pin FineLine BGA
672-pin BGA
780-pin FineLine BGA Transmitter
Package
Table 2–37
EP1S10, EP1S20, and EP1S25 devices.
show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Receiver
Transmitter
Receiver
Receiver
Receiver
Transmitter
Receiver
Receiver
Transmitter/
Receiver
shows the number of channels that each fast PLL can clock in
(2)
(2)
(2)
(2)
(2)
(2)
Channels
Total
20
20
36
36
44
44
24
20
48
50
66
66
Maximum
840
840
840
840
624
624
624
624
840
840
840
840
840
840
840
840
624
624
624
624
840
840
840
840
(Mbps)
Speed
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
Tables 2–38
Stratix Device Handbook, Volume 1
PLL 1
10
10
18
18
11
22
11
22
12
10
12
24
13
25
17
33
17
33
5
5
9
9
6
5
Center Fast PLLs
PLL 2
through
Note (1)
10
10
18
18
11
22
11
22
12
10
12
24
12
25
16
33
16
33
5
5
9
9
6
5
Stratix Architecture
PLL 3
Table 2–41
10
10
18
18
11
22
11
22
12
10
12
24
12
25
16
33
16
33
5
5
9
9
6
5
PLL 4
2–131
10
10
18
18
11
22
11
22
12
10
12
24
13
25
17
33
17
33
5
5
9
9
6
5
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