EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 707
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 707 of 864
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Altera Corporation
July 2005
device with the altclklock megafunction, there are specific cases
where you must use the altpll megafunction, as explained in this
section.
In the MegaWizard Plug-In Manager, select the altpll megafunction in
the I/O directory from the Available Megafunctions box (see
Figure
Quartus II software for backward compatibility, but instantiates the new
altpll megafunction when targeting Stratix or Stratix GX devices. The
Quartus II Compiler automatically selects whether the altpll module
uses either an enhanced PLL or a fast PLL based on the design’s PLL
needs and the feature requirements of each PLL.
Figure 10–9. altpll Megafunction Selection in the MegaWizard Plug-In
Manager
You can compile APEX II, APEX 20KE, and APEX 20KC designs using the
altclklock megafunction in normal mode for Stratix and Stratix GX
devices without updating the megafunction. However, you should
replace the altclklock megafunction with the altpll megafunction.
If the Quartus II software cannot implement the requested clock
multiplication and division of the PLL, the compiler reports an error
message with the appropriate reason stated.
10–9). The altclklock megafunction is also available from the
Transitioning APEX Designs to Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
10–23
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