EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 354

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Clocking
1–44
Stratix Device Handbook, Volume 2
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
Table 1–15. Stratix Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 1 of 2)
Network
Clock
PLL 1
(1)
v
v
v
v
v
v
v
v
PLL 2
(1)
v
v
v
v
v
v
v
v
Table 1–15
outputs to for Stratix devices.
clock network each of the CLK and
the PLL.
PLL 3
All Devices
(1)
v
v
v
v
PLL 4
(1)
v
v
v
v
shows the global and regional clocks that each PLL drives
PLL 5
(2)
v
v
v
v
v
v
PLL 6
(2)
v
v
v
v
Table 1–16
PLL 7
EP1S30, EP1S40, EP1S60 &
(1)
v
v
v
v
v
v
EP1S80 Devices Only
FPLLCLK
PLL 8
(1)
v
v
v
v
v
v
shows the global and regional
pins drive when bypassing
9
PLL
v
v
v
v
(1)
10
PLL
v
v
v
v
(1)
Altera Corporation
11
Devices Only
EP1S40 (5),
PLL
v
v
v
v
v
v
EP1S60 &
EP1S80
(2)
July 2005
12
PLL
v
v
v
v
(2)