EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 541

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number:
EP1S20F780I6N
Manufacturer:
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Quantity:
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Part Number:
EP1S20F780I6N
Manufacturer:
Altera
Quantity:
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Part Number:
EP1S20F780I6N
Manufacturer:
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Altera Corporation
July 2005
Figure 5–43. Page 4 of the Transmitter altlvds MegaWizard Plug-In Manager
Registered Inputs
Check the Register inputs box if the input data to the transmitter is not
registered just before it feeds the transmitter module. You can choose
either tx_clkin or tx_coreclk to clock the transmitter data
(tx_in[]) signal. This serves as the register boundary. The number of
registers used is proportional to the deserialization factor (J). The
Quartus II software places the synchronization registers with the LEs in
the same row and closest to the SERDES circuitry.
Use Common PLL for Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and receiver in the same I/O bank in Stratix devices. The
Quartus II software also allows the transmitter and receiver to share the
PLL when the same input clock is used for both. Although you must
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Device Handbook, Volume 2
5–69

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