EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 291
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 291 of 864
- Download datasheet (11Mb)
Stratix Device Handbook, Volume 1
Interconnect
IOE
J
JTAG
L
LAB
LUT
Altera Corporation
C4 Connections
DSP Block Interface to Interconnect
Left-Facing
LUT
M-RAM
R4 Connections
Internal Timing Microparameters
Boundary-Scan
Stratix JTAG
Control Signals
Wide Control Signals
Chain & Register Chain
Row I/O Block Connection to the
Row Pin
Signal Path through the I/O Block
SSTL-18
SSTL-2
SSTL-3 4–12,
Stratix
Supported I/O Standards
Transmitter Output Waveforms for Differ-
Column
Row Unit Interface to Interconnect
Register Length
Support
Instructions
Waveforms
Interface
Interconnects
I/O Standards
Interconnect
Configuration
ential I/O Standards
Interconnect
Input Delay Adders
Chain
4–12
IOE
4–11
3–1
M-RAM
3–4
2–40
3–2
Unit
2–5
4–13
2–18
2–15
in
3–3
2–17
2–6
2–106
2–42
Register
Bidirectional
2–110
4–5
2–8
to
Interface
2–123
4–6
4–67
Interconnect
4–29
2–72
Chain
2–108
2–41
I/O
to
M
Memory Architecture
Byte Enable for M4K
Byte Enable for M-RAM
External RAM Interfacing
M4K
M512
Memory Block Size
Memory Modes
M-RAM
RAM Block
Block
Block Internal Timing
RAM Block
Block Internal Timing
RAM Block
Block
Block Control Signals
Block Internal Timing
Combined
Microparameter
Microparameters
Configurations
Configurations
Control Signals
LAB Row Interface
Microparameter
Microparameters
Architecture
Configurations (Simple Dual-Port
Control Signals
LAB Row Interface
Configurations
Configurations
Microparameter
2–32
2–35
2–30
2–34
Byte
2–21
Descriptions
Port)
Port)
Descriptions
RAM)
Port)
Port)
Descriptions
2–26
Selection
2–27
2–37
2–31
2–31
2–34
2–35
2–115
2–27
2–33
2–29
(Simple
(Simple
4–31
(True
4–30
(True
2–33
2–30
4–24
4–24
4–25
for
Index–5
Dual-
Dual-
Dual-
Dual-
x144
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