EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 357

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S20F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
Notes to
(1)
(2)
RCLK13
RCLK14
RCLK15
Table 1–16. Stratix CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks
Clock Network
The CLK and FPLLCLK pins cannot drive.
The FPLLCLK pin is only available in EP1S80, EP1S60, EP1S40, and EP1S30 devices.
Table
1–16:
0
1
2
The fast PLLs also drive high-speed SERDES clocks for differential I/O
interfacing. For information on these FPLLCLK pins, see the High-Speed
Differential I/O Interfaces in Stratix Devices chapter.
Figure 1–21
connections from the enhanced.
information as
each specific PLL output port drives to.
3
4
5
shows the global and regional clock input and output
Tables 1–15
6
CLK Pins
v
7
General-Purpose PLLs in Stratix & Stratix GX Devices
v
8
and
v
9
1–16
10 11 12 13 14 15
Figure 1–21
but with the added detail of where
Stratix Device Handbook, Volume 2
shows graphically the same
7
FPLLCLK
8
Note (1)
9
(2)
1–47
10

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