EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 587
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 587 of 864
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Figure 7–4. Quartus II Software View of MegaWizard Implementation of a DSP Block in Four-Multipliers
Adder Mode
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Each input register of the DSP block provides a shiftout output that
connects to the shiftin input of the adjacent input register of the same DSP
block. The registers on the boundaries of a DSP block also connect to the
registers of adjacent DSP blocks through the use of shiftin/shiftout
connections. These connections create register chains spanning multiple
DSP blocks, which makes it easy to increase the length of FIR filters.
Figure 7–5
Filters with more taps can be implemented by connecting DSP blocks in
a similar manner, provided sufficient DSP blocks are available in the
device.
1
The input data can be fed directly or by using the shiftout/shiftin chains,
which allow a single input to shift down the register chain inside the DSP
block. The input to each of the registers has a multiplexer, hence, the data
can be fed either from outside the DSP block or the preceding register.
This can be selected from the MegaWizard
as shown in
shiftout/shiftin flip-flop chains where the multiplexers are configured to
use these chains. In this example, the flip-flops inside the DSP blocks
serve as the taps of the FIR filter.
Adding the outputs of the two DSP blocks requires an external
adder which can be implemented using logic cells.
shows two DSP blocks connected to create an 8-tap FIR filter.
Figure
7–4. The example in
Stratix Device Handbook, Volume 2
Figure 7–5
®
in the Quartus
uses the
®
II software,
7–9
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