EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 665

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 8–16. Stratix GX XAUI Implementation
I/O
Characteristics
for XSBI, XGMII
& XAUI
Altera Corporation
July 2005
Stratix GX XAUI
Logic Array
Stratix GX
8
8
8
8
information on XAUI support in Section II, Stratix GX Transceiver User
Guide of the Stratix GX Device Handbook, Volume 2.
XAUI is implemented.
The three interfaces of 10-Gigabit Ethernet (XSBI, XGMII, and XAUI) each
have different rates and I/O standards.
characteristics for each interface.
XGMII
XSBI
XAUI
Table 8–9. 10-Gigabit Ethernet Interfaces Characteristics
Interface
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
CDR Rx
CDR Rx
CDR Tx
CDR Tx
32
16
4
Width
CH0
CH3
156.25
644.5 or
622.08
None
CH0
CH3
Clock Rate
(MHz)
Per Channel
312.5 Mbps
644.5 or
622.08
Mbps
3.125 Gbps
Data Rate
Stratix Device Handbook, Volume 2
3.125 Gbps
Table 8–9
RX_D[0]
RX_D[3]
TX_D[0]
TX_D[3]
Figure 8–16
DDR source
synchronous
SDR source
synchronous
Clock data
recovery
(CDR)
shows the
Clocking
Scheme
Transmitter
PCS
shows how
Receiver
1.5-V
HSTL
LVDS
1.5-V
PCML
I/O Type
8–21