EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 469

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S20F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
0
Figure 4–24. Floorplan View Window
Altera Corporation
June 2006
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the placement for all I/O
and V
Automatically places I/O pins of different V
pin assignments in separate I/O banks and enables the V
these I/O banks.
Verifies that voltage-referenced I/O pins requiring different V
levels are not placed in the same bank.
Reports an error message if the current limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in
Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differential I/O banks when
any of the high-speed differential I/O channels are being used.
Automatically assigns V
requirements are met and I/O standards are placed properly.
REF
pins and performs the following actions.
Selectable I/O Standards in Stratix & Stratix GX Devices
“DC Guidelines” on page
REF
pins and I/O pins such that the current
Stratix Device Handbook, Volume 2
4–35.
REF
standards without
REF
pins of
REF
4–41

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