EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 610
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Finite Impulse Response (FIR) Filters
7–32
Stratix Device Handbook, Volume 2
where:
In complex representation, this equals:
The overall real channel output is obtained by adding the real channel
outputs of all the multipliers. Similarly, the overall imaginary channel
output is obtained by adding the imaginary channel outputs of all the
multipliers.
Figure 7–18. Complex FIR Filter Block Diagram
Complex FIR Filter Implementation
Complex filters can be easily implemented in Stratix devices with the DSP
blocks configured in the two-multipliers adder mode. One DSP block can
implement a 2-tap complex FIR filter with 9-bit inputs, or a single tap
complex FIR filter with 18-bit inputs. DSP blocks can be cascaded to
implement complex filters with more taps.
1
x
x
h
h
y
y
y
y
y
real
imag
real
imag
real
imag
real
imag
real
is the real input signal
is the real filter coefficients
is the real output signal
The two-multipliers adder mode has two adders, each adding
the outputs of two multipliers. One of the adders is configured
as a subtractor.
is the imaginary input signal
is the imaginary filter coefficients
is the imaginary output signal
+
=
=
jy
x
imag
x
real
real
x imag
x real
=
h
h
real
x
imag
real
–
+
+
x
imag
h
jx
real
imag
h real
Complex
FIR filter
h
x
imag
imag
h imag
h
real
+
jh
imag
y real
y imag
Altera Corporation
September 2004
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