EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 380

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Using TriMatrix Memory
2–12
Stratix Device Handbook, Volume 2
4K
2K
1K
512
256
512
256
Table 2–10. M4K Block Mixed-Port Width Configurations (True Dual-Port)
1
2
4
8
16
9
18
Port A
4K
Figure 2–6. True Dual-Port Memory
Note to
(1)
The widest bit configuration of the M4K and M-RAM blocks in true dual-
port mode is 256
with parity), respectively. The 128
configuration of the M4K block and the 4K
configuration of the M-RAM block are unavailable because the number of
output drivers is equivalent to the maximum bit width of the respective
memory block. Because true dual-port RAM has outputs on two ports,
the maximum width of the true dual-port RAM equals half of the total
number of output drivers.
RAM block and M-RAM block configurations, respectively.
v
v
v
v
v
1
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
Figure
2K
v
v
v
v
v
2–6:
2
data
address
wren
clocken
q
aclr
16-bit ( 18-bit with parity) and 8K
A
1K
clock
[ ]
A
v
v
v
v
v
A
A
[ ]
A
A
A
4
[ ]
A
Tables 2–10
512
Port B
Note (1)
v
v
v
v
v
32-bit ( 36-bit with parity)
8
and
256
2–11
128-bit ( 144-bit with parity)
v
v
v
v
v
B
address
clocken
clock
16
data
list the possible M4K
wren
aclr
q
B
B
B
B
[ ]
[ ]
[ ]
B
B
B
512
Altera Corporation
v
v
64-bit ( 72-bit
9
256
July 2005
v
v
18