EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 701

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
July 2005
APEX II and APEX 20K designs use pipeline stages to improve registered
performance of LE-based multipliers at the expense of latency. However,
you may not need to use pipeline stages when targeting Stratix and
Stratix GX high-speed DSP blocks. The DSP blocks offer three sets of
dedicated pipeline registers. Therefore, Altera recommends that you
reduce the number of pipeline stages to three or fewer and implement
them in the DSP blocks. Additional pipeline stages are implemented in
LEs, which add latency without providing any performance benefit.
For example, you can configure a DSP block for 36
using the lpm_mult megafunction. If you specify two pipeline stages,
the software uses the DSP block input and pipeline registers. If you
specify three pipeline stages, the software places the third pipeline stage
in the DSP block output registers. This design yields the same
performance with three pipeline stages because the critical path for a
36
stages, the device inefficiently uses LE resources for the additional
pipeline stages. Therefore, if multiplier modules in APEX II or APEX 20K
designs are converted to Stratix or Stratix GX designs and do not require
the same number of pipeline stages, the surrounding circuitry must be
modified to preserve the original functionality of the design.
A design with multipliers feeding an accumulator can use the
altmult_accum (MAC) megafunction to set the DSP block in multiply-
accumulator mode. If the APEX II or APEX 20K design already uses LE-
based multipliers feeding an accumulator, the Quartus II software does
not automatically instantiate the new altmult_accum (MAC)
megafunction. Therefore, you should use the MegaWizard Plug-In
Manager to instantiate the altmult_accum (MAC) megafunction. You
can also use LeonardoSpectrum
DSP block inference support, to instantiate the megafunction.
Designs that use multipliers feeding into adders can instantiate the new
altmult_add megafunction to configure the DSP blocks for two-
multipliers adder or four-multipliers adder mode. You can also use the
altmult_add megafunction for stand-alone multipliers to take
advantage of the DSP blocks features such as dynamic sign control of the
inputs and the input shift register connections. These features are not
accessible through the lpm_mult megafunction. If your APEX II or
APEX 20K designs already use multipliers feeding an adder/subtractor,
the Quartus II software does not automatically infer the new
altmult_add megafunction. Therefore, you should step through the
MegaWizard Plug-In Manager to instantiate the new altmult_add
megafunction or use LeonardoSpectrum or Synplify synthesis tools,
which have DSP block inference support.
36-bit operation is within the multiplier. With four or more pipeline
Transitioning APEX Designs to Stratix & Stratix GX Devices
™
or Synplify synthesis tools, which have
Stratix Device Handbook, Volume 2
36-bit multiplication
10–17