EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 672

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Introduction
9–2
Stratix Device Handbook, Volume 2
The SONET/SDH specification outlines the frame format, multiplexing
method, synchronization method, and optical interface between the
equipment, as well as the specific optical interface.
SONET/SDH continues to play a key role in the next generation of
networks for many carriers. In the core network, the carriers offer services
such as telephone, dedicated leased lines, and Internet protocol (IP) data,
which are continuously transmitted. The individual data channels are not
transmitted on separate lines; instead, they are multiplexed into higher
speeds and transmitted on SONET/SDH networks at the corresponding
transmission speed.
Figure 9–2
as follows:
1.
2.
3.
4.
5.
6.
7.
The SONET/SDH line card first takes a high-speed serial optical
signal and converts it into a high-speed serial electrical signal. The
devices are called physical media dependent (PMD) devices.
The system then recovers the clock from the electrical data using a
clock data recovery (CDR) unit.
The SERDES parallelizes the data so that it can be manipulated
easily at lower clock rates.
The interface between the SERDES and framer is called the SERDES
framer interface. The interface requirements are defined by the OIF.
The framer identifies the beginning of the SONET/SDH frames and
monitors the performance of the system.
The mapper following the framer maps asynchronous transfer
mode (ATM) cells, IP packets, or T/E carrier signals into the SONET
frame.
The PHY-link layer interface provides a bus interface to packet/cell
processors or other link-layer devices.
shows a typical SONET/SDH line card. The system operates
Altera Corporation
July 2005