EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 584

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Finite Impulse Response (FIR) Filters
Figure 7–2. Basic FIR Filter
7–6
Stratix Device Handbook, Volume 2
h(0)
x(n)
h(1)
h(2)
FIR Filter Background
Digital communications systems use FIR filters for a variety of functions,
including waveform shaping, anti-aliasing, band selection,
decimation/interpolation, and low pass filtering. The basic structure of a
FIR filter consists of a series of multiplications followed by an addition.
The following equation represents an FIR filter operation:
where:
A sample FIR filter with L=8 is shown in
This example filter in
time instants to produce an output. Hence, it is an 8-tap filter. Each
register provides a unit sample delay. The delayed inputs are multiplied
with their respective filter coefficients and added together to produce the
output. The width of the output bus depends on the number of taps and
the bit width of the input and coefficients.
x(n) represents the sequence of input samples
h(n) represents the filter coefficients
L is the number of filter taps
y n
y n
=
=
h(3)
x n
L 1
i
=
–
0
x n i – h i
h n
Figure 7–2
h(4)
y(n)
uses the input values at eight different
h(5)
Figure
h(6)
7–2.
Altera Corporation
September 2004
h(7)