EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 288
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 288 of 864
- Download datasheet (11Mb)
Index–2
Global & Hierarchical Clocking
Global & Regional Clock Connections
Global
Global Clock Network
Global Clocking
Independent Clock Mode
Input/Output
Maximum Input & Output Clock Rates
Maximum Input Clock Rate
Maximum Output Clock Rate
from Side Pins & Fast PLL Outputs
from Top Clock Pins & Enhanced PLL
Clock Mode
for CLK
for PLL
Parameters
Outputs
Clock
Simple Dual-Port Mode
True Dual-Port Mode
(0, 2, 9, 11) Pins in
(1, 3, 8, 10) Pins in
(7..4) & CLK(15..12) Pins in
(1, 2, 3, 4) Pins in
(5, 6, 11, 12) Pins in
2–46
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
Wire-Bond
Flip-Chip
2–75
External
4–35
2–86
Packages
Packages
Packages
Packages
Packages
Packages
Packages
Packages
2–74
2–44
I/O
2–73
2–47
2–48
4–77
4–79
4–78
4–80
4–76
4–78
4–83
4–85
Timing
2–85
4–76
Configuration
Control Signals
D
DC Switching
DDR
Device Features
Phase & Delay Shifting
Phase Delay
PLL Clock Networks
Read/Write Clock Mode
Regional Clock
Regional Clock Bus
Regional Clock Network
Spread-Spectrum Clocking
32-Bit IDCODE
and Testing
Data Sources for Configuration
Local Update Mode
Local Update Transition Diagram
Operating Modes
Partial Reconfiguration
Remote Update
Remote Update Transition Diagram
Schemes
SignalTap II Embedded Logic Analyzer
Stratix FPGAs with JRunner
Absolute Maximum Ratings
Bus Hold Parameters
Capacitance
DC & Switching Characteristics
External Timing Parameters
Operating Conditions
Performance
Power Consumption
Recommended Operating Conditions
Double-Data Rate I/O Pins
EP1S10, EP1S20, EP1S25, EP1S30,
EP1S40, EP1S60, EP1S80,
in Simple Dual-Port Mode
External I/O Timing Parameters
2–49
3–7
Stratix Device Handbook, Volume 1
3–5
3–1
4–17
2–96
2–104
Wire-Bond
4–20
2–75
3–3
3–8
3–5
2–79
3–12
4–17
2–73
4–16
Packages
Packages
4–1
2–96
3–7
2–75
1–3
Altera Corporation
2–98
2–111
3–7
4–33
4–1
2–50
3–7
4–1
1–3
3–12
4–81
4–84
4–34
3–11
4–1
3–5
Related parts for EP1S20F780I6N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: