EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 599

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
required is 16
number of computations per cycle required is 4
there are four polyphase filters, each with four taps.
Figure 7–12. Polyphase Representation of I=4 Interpolation Filter
Polyphase Interpolation Filter Implementation
Figure 7–13
polyphase interpolation filter in
share the same hardware, which is a 4-tap filter. One Stratix or Stratix GX
DSP block can implement one 4-tap filter with 18-bit wide data and
coefficients. A multiplexer can be used to load new coefficient values on
every cycle of the 4 clock. Stratix and Stratix GX phase lock loops (PLLs)
can generate the 4 clock. In the first cycle of the 4 clock, the user needs
to load coefficients for polyphase filter h
Interpolation Using a Single Low-Pass Filter
Interpolation Using a Polyphase Filter
Input
Input
x(n)
x(n)
shows the Stratix or Stratix GX implementation of the
I = 16
I = 4
h(2), h(6), h(10), h(14)
h(3), h(7), h(11), h(15)
h(0), h(4), h(8), h(12)
h(1), h(5), h(9), h(13)
with coefficients
with coefficients
with coefficients
with coefficients
Polyphase filter
Polyphase filter
Polyphase filter
Polyphase filter
4 = 64. In the polyphase implementation, the
Figure
4x Clock
h(0), h(1), ... h(15)
coefficients
y4(n)
y1(n)
y2(n)
y3(n)
Stratix Device Handbook, Volume 2
7–12. The four polyphase filters
0
LPF with
(n); in the second cycle of the 4
initialized at 0
Modulo 4 up
counter
4 = 16. This is because
0
2
3
1
Output
y(n)
Output
y(n)
7–21