EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 351

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
July 2005
RCLK[12..15] are in the bottom-right quadrant. The regional clock
networks only pertain to the quadrant they drive into. The regional clock
networks provide the lowest clock delay and skew for logic contained
within a single quadrant. RCLK clock networks cannot be driven by
internal logic. The CLK clock pins symmetrically drive the RCLK networks
within a particular quadrant, as shown in
and
Figure 1–20. Regional Clocks
Clock Input Connections
Two CLK pins drive each enhanced PLL. You can use either one or both
pins for clock switchover inputs into the PLL. Either pin can be the
primary clock source for clock switchover, which is controlled in the
Quartus II software. Enhanced PLLs 5 and 6 also have feedback input
pins as shown in
RCLK[1..0]
RCLK[4..5]
1–22
CLK[3..0]
for RCLK connections from PLLs and CLK pins.
Table
General-Purpose PLLs in Stratix & Stratix GX Devices
1–14.
RCLK[6..7]
RCLK[2..3]
CLK[7..4]
RCLK[12..13]
RCLK[11..10]
CLK[15..12]
Stratix Device Handbook, Volume 2
Figure
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
1–20. See
CLK[11..8]
Figures 1–21
RCLK[14..15]
RCLK[9..8]
1–41