EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 556
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Architecture
6–6
Stratix Device Handbook, Volume 2
Input Registers
Each operand feeds an input register or the multiplier directly. The DSP
block has the following signals (one of each controls every input and
output register):
■
■
■
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The shift outputs from one
multiplier block directly feed the adjacent multiplier block in the same
DSP block (or the next DSP block), as shown in
form a shift register chain. This chain can terminate in any block, i.e., you
can create any length of shift register chain up to 224 registers. A shift
register is useful in DSP applications such as FIR filters. When
implementing 9
logic to create the shift register chain because the input shift registers are
internal to the DSP block. This implementation greatly reduces the
required LE count and routing resources, and produces repeatable
timing.
clock[3..0]
ena[3..0]
aclr[3..0]
9 and 18
18 multipliers, you do not need external
Figure 6–4 on page
Altera Corporation
July 2005
6–7, to
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