EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 576

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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0
Operational Modes
6–26
Stratix Device Handbook, Volume 2
FIR Filters
The four-multiplier adder mode can be used for FIR filter and complex
FIR filter applications. The DSP block combines a four-multiplier adder
with the input registers configured as shift registers. One set of shift
inputs contains the filter data, while the other holds the coefficients,
which can be loaded serially or in parallel (see
The input shift register eliminates the need for shift registers external to
the DSP block (e.g., implemented in device logic elements). This
architecture simplifies filter design and improves performance because
the DSP block implements all of the filter circuitry.
1
One DSP block can implement an entire 18-bit FIR filter with up to four
taps. For FIR filters larger than four taps, you can cascade DSP blocks
with additional adder stages implemented in logic elements.
Serial shift inputs in 36-bit simple multiplier mode require
external registers.
Figure
6–15).
Altera Corporation
July 2005

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