EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 498

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Receiver Data Realignment
Figure 5–18. SERDES Function Timing Diagram in Normal Operation
5–26
Stratix Device Handbook, Volume 2
Serial data
×8 clock
×1 clock
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
D7
D0
D1
D2
RXLOADEN signal and dropping the first incoming bit of the serial input
data stream located in the first serial register of the SERDES circuitry
(shown in
Figure 5–18
normal
a Stratix SERDES when data realignment is used.
D3
D2
D3
D4
D5
D6
D7
D0
D1
D4
×
8 mode, and
Figure 5–3 on page
D5
shows the function-timing diagram of a Stratix SERDES in
D6
D7
Figure 5–19
D0
D1
5–8).
D2
shows the function-timing diagrams of
D3
D2
D3
D4
D5
D6
D7
D0
D1
D4
D5
D6
Altera Corporation
D7
D0
July 2005
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2