EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 494

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Differential I/O Interface & Fast PLLs
Figure 5–15. Fast PLL Connection to Logic Array
5–22
Stratix Device Handbook, Volume 2
VCO Phase Selection
Selectable at each PLL
Output Port
PLL Output
Counter Circuitry
The multiplied clocks bypass the counter taps k and v to directly feed the
SERDES serial registers. These two taps also feed to the quadrant local
clock network and the dedicated RXLOADENA or TXLOADENA pins, as
shown in
data-realignment procedure. When the design does not use the data
realignment, both TXLOADEN and RXLOADEN pins use a single counter.
The Stratix device fast PLL has another GCLK connection for general-
purpose applications. The third tap l feeds the quadrant local clock as
well as the global clock network. You can use the l counter's multiplexer
for applications requiring the device to connect the incoming clock
directly to the local or global clocks. You can program the multiplexer to
connect the RXCLKIN signal directly to the local or global clock lines.
Figure 5–15
and the local or global clock lines.
The differential clock selection is made per differential bank. Since the
length of the clock tree limits the performance, each fast PLL should drive
only one differential bank.
Counter Circuitry
8
Figure
shows the connection between the incoming clock, the l tap,
Post-Scale
clkin
Counters
5–15. Both k and v are utilized simultaneously during the
÷ k
÷ v
÷ l
Clock
Distribution
Circuitry
CLK1 SERDES
Circuitry
×1 CLK1 to logic array
or local clocks
TXLOADEN
RXLOADEN
×1 CLK2 to logic array
or local clocks
CLK2 SERDES
Circuitry
Regional clock
Altera Corporation
July 2005