EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 656
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Interfaces
Figure 8–9. PCS Receiver Timing Diagram
8–12
Stratix Device Handbook, Volume 2
PMA_TX_CLK
PMA_TX_CLK
Data invalid window before the rising edge
(T
Data invalid window after the rising edge (T
PMA_TX_CLK
PCS transmitter channel-to-channel skew
PMA_RX_CLK
PMA_RX_CLK
Data invalid window before the rising edge (T
Data invalid window after the rising edge (T
RX_DATA[15..0]
Table 8–4. PCS Transmitter Timing Specifications
Table 8–5. PCS Receiver Timing Specifications (Part 1 of 2)
PMA_RX_CLK
cq_pre
)
T cq_pre
T
T
duty cycle
T
T
period
period
period
period
Parameter
Parameter
(WAN)
(LAN)
(WAN)
(LAN)
T cq_post
Valid
Data
Table 8–4
Figure 8–9
PCS receiver interface. You can determine the PCS sampling window by
adding T
of skew tolerated on the printed circuit board (PCB).
Table 8–5
T period
T setup
setup
lists the AC timing specifications for the PCS transmitter.
lists the AC timing specifications for the PCS receiver interface.
shows the AC timing diagram for the Stratix and Stratix GX
cq_post
cq_post
to T
T hold
cq_pre
)
hold
)
)
. Receiver skew margin (RSKM) refers to the amount
Transmitter Channel-to-Channel
RX_DATA[15..0]
Min
PMA_RX_CLK
40
Min
Skew/2
Value
1,608
1,552
Value
Typ
1,608
1,552
Typ
RSKM
Sampling Window
T period
Max
200
200
200
Max
60
RSKM
200
200
Altera Corporation
Transmitter Channel-to-Channel
Skew/2
July 2005
Unit
Unit
ps
ps
ps
ps
ps
%
ps
ps
ps
ps
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