EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 745
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
July 2005
Figure 11–12. Parallel Configuration Using a Microprocessor
Note to
(1)
For multi-device parallel configuration with a microprocessor, the nCEO
pin of the first Stratix or Stratix GX device is cascaded to the second
device’s nCE pin. The second device in the chain begins configuration
within one clock cycle; therefore, the transfer of data destinations is
transparent to the microprocessor. Because the CONF_DONE pins of the
devices are connected together, all devices initialize and enter user mode
at the same time.
Because the nSTATUS pins are also tied together, if any of the devices
detects an error, the entire chain halts configuration and drives nSTATUS
low. The microprocessor can then pulse nCONFIG low to restart
configuration. If the Auto-restart configuration after error option is on,
the Stratix and Stratix GX devices release nSTATUS after a reset time-out
period. The microprocessor can then reconfigure the devices once
nSTATUS is released.
using a microprocessor.
when both Stratix and Stratix GX devices are receiving the same data. In
this case, the microprocessor sends the data to both devices
simultaneously, and the devices configure simultaneously.
Microprocessor
The pull-up resistors should be connected to any V
level input voltage (V
ADDR DATA[7..0]
Figure
Memory
11–12:
Figure 11–13
IH
) specification.
Figure 11–14
Configuring Stratix & Stratix GX Devices
shows multi-device configuration
V
CC
10 kΩ
shows multi-device configuration
(1)
Stratix Device Handbook, Volume 2
GND
V
CC
10 kΩ
(1)
CC
that meets the Stratix high-
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Stratix Device
MSEL2
MSEL1
MSEL0
nCEO
GND
11–27
N.C.
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