EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 617

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
Basic IIR Filter Implementation Results
Table 7–15
Stratix device.
Basic IIR Filter Design Example
Download the 4
Design Examples section of the Altera web site at www.altera.com.
Butterworth IIR Filters
Butterworth filters are the most popular version of IIR analog filters.
These filters are also known as “maximally flat” because they have no
passband ripple. Additionally, they have a monotonic response in both
the stopband and the passband. Butterworth filters trade-off roll off
steepness for their no ripple characteristic. The distinguishing
Butterworth filter feature is its poles are arranged in a uniquely
symmetrical manner along a circle in the s-plane. The expression for the
Butterworth filter’s magnitude-squared function is as follows:
where:
The filter’s cutoff characteristics become sharper as N increases. If a
substitution is made such that j = s, then the following equation is
derived:
Part
Utilization
Performance
Latency
Table 7–15. 4
N is the filter order
H
c
is the cut-off frequency
c
j
shows the results of implementing a 4
2
th
=
Order IIR Filter Implementation Results
th
--------------------------- -
1
Order IIR Filter (iir.zip) design example from the
+
------ -
j
1
EP1S10F780C5
Lcell: 102/10570(<1%)
DSP Block 9-bit elements: 24/48 (50%)
Memory bits: 0/920448(0%)
73 MHz
4 clock cycles
j
c
2N
Stratix Device Handbook, Volume 2
th
order IIR filter in a
7–39