EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 542

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Software Support
5–70
Stratix Device Handbook, Volume 2
separate the transmitter and receiver in your design, the Quartus II
software merges the fast PLLs when appropriate and gives you the
following message:
Receiver fast PLL <lvds_rx pll name> and transmitter fast PLL
<lvds_tx pll name> are merged together
The Quartus II software gives the following message when it cannot
merge the fast PLLs for the LVDS transmitter and receiver pair in the
design:
tx_outclock Resource
You can use either the global or regional clock for the tx_outclock
signal. If you select Auto in the Quartus II software, the tool uses any
available lines.
SERDES Bypass Mode
You can bypass the SERDES block if your data rate is less than 624 Mbps,
and you must bypass the SERDES block for the
Since you cannot route the fast PLL output to an output pin, you must
create additional DDR I/O circuitry for the transmitter clock output. To
create an
megafunction clocked by the
and datain_l connected to GND.
×1 Mode
For
the Quartus II software that you are using differential signaling.
However, Altera recommends using the DDRIO circuitry when the input
or output data rate is higher than 231 Mbps. The maximum output clock
frequency for
×2 Mode
You must use the DDRIO circuitry for
provides the altddio_in and altddio_out megafunctions to use for
×
×
circuitry in
2 receiver and
2 mode is 624 Mbps.
×
Can't merge transmitter-only fast PLL
<lvds_tx pll name> and receiver-only fast PLL
<lvds_rx pll name>
1 mode, you only need to specify the I/O standard of the pins to tell
×
J transmitter output clock, instantiate an alt_ddio
×
2 mode.
×
1 mode is 420 MHz.
×
2 transmitter, respectively. The maximum data rate in
Figure 5–44
×
J clock with datain_h connected to V
shows the schematic for using DDR
×
2 mode. The Quartus II software
×
1 and
×
Altera Corporation
2 LVDS modules.
July 2005
CC