EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 416
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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DDR Memory Support Overview
3–20
Stratix Device Handbook, Volume 2
DDR Registers
Each Stratix and Stratix GX IOE contains six registers and one latch. Two
registers and a latch are used for input, two registers are used for output,
and two registers are used for output enable control. The second output
enable register provides the write preamble for the DQS strobe in the
DDR external memory interfaces. This negative-edge output enable
register extends the high-impedance state of the pin by a half clock cycle
to provide the external memory's DQS preamble time specification.
Figure 3–10
Stratix GX IOE and
extends the DQS high impedance state by half a clock cycle during a write
operation.
shows the six registers and the latch in the Stratix and
Figure 3–11
shows how the second OE register
Altera Corporation
June 2006
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