EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 476

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Stratix I/O Banks
5–4
Stratix Device Handbook, Volume 2
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard requiring a 3.3-V
V
data transfer, backplane drivers, and clock distribution. The
ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers
capable of operating at recommended maximum data signaling rates of
655 Mbps. However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix devices meet the
ANSI/TIA/EIA-644 standard.
Due to the low voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than CMOS,
transistor-to-transistor logic (TTL), and PECL. This low EMI makes LVDS
ideal for applications with low EMI requirements or noise immunity
requirements. The LVDS standard specifies a differential output voltage
range of 0.25 V
input reference voltage, however, it does require a 100- termination
resistor between the two signals at the input buffer. Stratix devices
include an optional differential termination resistor within the device. See
Section I, Stratix Device Family Data Sheet
Volume 1
HyperTransport Technology
The HyperTransport technology I/O standard is a differential high-
speed, high-performance I/O interface standard requiring a 2.5-V
VCCIO. This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport
technology I/O standard is a point-to-point standard in which each
HyperTransport technology bus consists of two point-to-point
unidirectional links. Each link is 2 to 32 bits. See the Stratix Device Family
Data Sheet section of the Stratix Device Handbook, Volume 1 for the
HyperTransport parameters.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V V
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. See the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1
for the LVPECL signaling characteristics.
CCIO
. This standard is used in applications requiring high-bandwidth
CCIO.
for the LVDS parameters.
The standard is used in applications involving video
×
V
OD
0.45 V. The LVDS standard does not require an
of the
Stratix Device Handbook,
Altera Corporation
July 2005