EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 601

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 7–13. Implementation of the Polyphase Interpolation Filter (I=4)
Notes to
(1)
(2)
(3)
Altera Corporation
September 2004
Clock input
(1x clock)
The 1
The 4 clock feeds the input registers for the filter coefficients and other optional registers in the DSP block. See
Note
To increase the DSP block performance, include the pipeline, and output registers. See
Figure
(3).
clock feeds the input data shiftin register chain.
7–13:
PLL
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
1x clock
4x clock
Filter coefficients
RAM / ROM 0
RAM / ROM 2
RAM / ROM 1
Data input
h(3)
h(2)
h(0)
h(1)
x(n)
x x
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
Stratix Device Handbook, Volume 2
Notes
(1), (2),
Note (1)
Figure 7–3
DSP block
(3)
Note (2)
for the details.
Filter output
y(n)
7–23