h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1053
h8s-2635
Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2635.pdf
(1547 pages)
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23B.6.2 Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pins
means of the
23B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator:
1. Setting for H8S/2636, H8S/2638, H8S/2639, H8S/2630
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
Clearing with an interrupt
When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
Clearing with the
When the
oscillation starts, clocks are supplied to the entire chip. Note that the
Low until clock oscillation stabilizes. When the
exception handling.
Clearing with the
When the
Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization
time).
Table 23B-6 shows the standby times for different operating frequencies and settings of bits
STS2 to STS0.
R E S
R E S
S T B Y
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
pin or
pin is driven Low, clock oscillation is started. At the same time as clock
pin is driven Low, a transition is made to hardware standby mode.
R E S
S T B Y
S T B Y
pin
pin
pin.
R E S
Rev. 6.00 Feb 22, 2005 page 993 of 1484
pin goes high, the CPU begins reset
R E S
I R Q 0
pin must be held
REJ09B0103-0600
to
I R Q 5
) , or by
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