h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 201

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h8s-2635

Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits
specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked.
Bit 6
CDA
0
1
Bit 5
BAMRA2 BAMRA1 BAMRA0 Description
0
1
Bit 4
0
1
0
1
Description
PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
Bit 3
0
1
0
1
0
1
0
1
All BARA bits are unmasked and included in break conditions
BAA0 (lowest bit) is masked, and not included in break
conditions
BAA1, BAA0 (lower 2 bits) are masked, and not included in
break conditions
BAA2 to BAA0 (lower 3 bits) are masked, and not included in
break conditions
BAA3 to BAA0 (lower 4 bits) are masked, and not included in
break conditions
BAA7 to BAA0 (lower 8 bits) are masked, and not included in
break conditions
BAA11 to BAA0 (lower 12 bits) are masked, and not included in
break conditions
BAA15 to BAA0 (lower 16 bits) are masked, and not included in
break conditions
Rev. 6.00 Feb 22, 2005 page 141 of 1484
Section 6 PC Break Controller (PBC)
REJ09B0103-0600
(Initial value)
(Initial value)

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