h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1404

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Appendix B Internal I/O Register
Rev. 6.00 Feb 22, 2005 page 1344 of 1484
REJ09B0103-0600
LPWRCR—Low-Power Control Register
Direct Transition ON Flag
Bit
Initial value
Read/Write
Note:
Note: 1. Bits 7 to 3 in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635 Group; they are
0
1
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-sleep mode or
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode, operation shifts
• When the SLEEP instruction is executed in sub-active mode, operation shifts directly to high-speed
*
to sleep mode, software standby mode, or watch mode*
watch mode
directly to sub-active mode*, or shifts to sleep mode or software standby mode
mode, or shifts to sub-sleep mode
Always set high-speed mode when shifting to watch mode or sub-active mode.
reserved bits in all other versions.
See sections 23A.2.3, 23B.2.3, Low-Power Control Register (LPWRCR), for more information.
DTON *
Note: * Always set high-speed mode when shifting to watch mode or sub-active mode.
Low-Speed ON Flag
0
1
R/W
7
0
• When the SLEEP instruction is executed in high-speed mode or medium-speed mode,
• When the SLEEP instruction is executed in sub-active mode, operation shifts to watch
• Operation shifts to high-speed mode when watch mode is cancelled
• When the SLEEP instruction is executed in high-speed mode, operation shifts to watch
• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
• Operation shifts to sub-active mode when watch mode is cancelled
operation shifts to sleep mode, software standby mode, or watch mode*
mode or shifts directly to high-speed mode
mode or sub-active mode
sleep mode or watch mode
1
LSON *
R/W
6
0
1
Noise Elimination Sampling Frequency Select
0
1
NESEL *
R/W
Sampling using 1/32 × φ
Sampling using 1/4 × φ
5
0
Subclock Enable
0
1
1
SUBSTP *
Enables subclock generation
Disables subclock generation
Oscillation Circuit Feedback Resistance Control Bit
0
1
R/W
4
0
When the main clock is oscillating, sets the feedback
resistance ON. When the main clock is stopped, sets
the feedback resistance OFF
Sets the feedback resistance OFF
1
RFCUT *
R/W
3
0
H'FDEC
1
R/W

2
0
Frequency Multiplication Factor
0
1
0
1
0
1
STC1
R/W
×1
×2
×4
Setting prohibited
1
0
STC0
R/W
0
0
System