h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1056

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
23B.6.5 Usage Notes
I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,
the address bus and bus control signal output is also retained. Therefore, there is no reduction in
current dissipation for the output current when a high-level signal is output.
Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation
increases during the oscillation stabilization wait period.
Write Data Buffer Function: The write data buffer function and software standby mode cannot
be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL
should be cleared to 0 to cancel the write data buffer function before entering software standby
mode. Also check that external writes have finished, by reading external addresses, etc., before
executing a SLEEP instruction to enter software standby mode. See section 7.9, Write Data Buffer
Function, for details of the write data buffer function.
23B.7 Hardware Standby Mode
23B.7.1 Hardware Standby Mode
When the
pin is driven low, a transition is made to hardware standby mode from any mode.
S T B Y
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the
pin low.
S T B Y
Do not change the state of the mode pins (MD2 to MD0) while the chip is in hardware standby
mode.
Hardware standby mode is cleared by means of the
pin and the
pin. When the
S T B Y
R E S
S T B Y
pin is driven high while the
pin is low, the reset state is set and clock oscillation is started.
R E S
Ensure that the
pin is held low until the clock oscillator stabilizes (at least 8 ms—the
R E S
oscillation stabilization time—when using a crystal oscillator). When the
pin is subsequently
R E S
driven high, a transition is made to the program execution state via the reset exception handling
state.
Rev. 6.00 Feb 22, 2005 page 996 of 1484
REJ09B0103-0600