h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 203

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.
6.3
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt
Due to Data Access, taking the example of channel A.
6.3.1
(1) Initial settings
(2) Satisfaction of break condition
(3) Interrupt handling
Bit 4
MSTPC4
0
1
Set the break address in BARA. For a PC break caused by an instruction fetch, set the
address of the first instruction byte as the break address.
Set the break conditions in BCRA.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, CSELA0): Set 00 to specify an instruction fetch as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
When the instruction at the set address is fetched, a PC break request is generated
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
Operation
PC Break Interrupt Due to Instruction Fetch
Description
PC break controller module stop mode is cleared
PC break controller module stop mode is set
Rev. 6.00 Feb 22, 2005 page 143 of 1484
Section 6 PC Break Controller (PBC)
REJ09B0103-0600
(Initial value)