h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 40

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 PC Break Controller (PBC)
6.1
6.2
6.3
Section 7 Bus Controller
7.1
7.2
7.3
Rev. 6.00 Feb 22, 2005 page xl of lx
5.6.3
Overview........................................................................................................................... 137
6.1.1
6.1.2
6.1.3
Register Descriptions........................................................................................................ 139
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Operation .......................................................................................................................... 143
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
Overview........................................................................................................................... 149
7.1.1
7.1.2
7.1.3
7.1.4
Register Descriptions........................................................................................................ 152
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
Overview of Bus Control.................................................................................................. 163
7.3.1
7.3.2
7.3.3
7.3.4
Operation ............................................................................................................. 134
Features................................................................................................................ 137
Block Diagram..................................................................................................... 138
Register Configuration......................................................................................... 139
Break Address Register A (BARA) ..................................................................... 139
Break Address Register B (BARB) ..................................................................... 140
Break Control Register A (BCRA) ...................................................................... 140
Break Control Register B (BCRB) ...................................................................... 142
Module Stop Control Register C (MSTPCRC) ................................................... 142
PC Break Interrupt Due to Instruction Fetch ....................................................... 143
PC Break Interrupt Due to Data Access .............................................................. 144
Notes on PC Break Interrupt Handling................................................................ 144
Operation in Transitions to Power-Down Modes ................................................ 145
PC Break Operation in Continuous Data Transfer............................................... 146
When Instruction Execution Is Delayed by One State......................................... 147
Additional Notes.................................................................................................. 148
Features................................................................................................................ 149
Block Diagram..................................................................................................... 150
Pin Configuration ................................................................................................ 151
Register Configuration......................................................................................... 151
Bus Width Control Register (ABWCR)............................................................... 152
Access State Control Register (ASTCR) ............................................................. 153
Wait Control Registers H and L (WCRH, WCRL).............................................. 154
Bus Control Register H (BCRH) ......................................................................... 158
Bus Control Register L (BCRL) .......................................................................... 160
Pin Function Control Register (PFCR) ................................................................ 161
Area Partitioning.................................................................................................. 163
Bus Specifications ............................................................................................... 164
Memory Interfaces............................................................................................... 165
Interface Specifications for Each Area ................................................................ 166
................................................................................................... 149
........................................................................... 137