h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1255

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Note: * This register is not available in the H8S/2635 and H8S/2634.
IRR0—Interrupt Register
IRR1—Interrupt Register
Overload Frame Interrupt Flag
Bit
Initial value
Read/Write
0
1
[Clearing condition]
• Writing 1
Overload frame transmission
[Setting condition]
• Overload frame is transmitted
Bus Off Interrupt Flag
0
1
[Clearing condition]
• Writing 1
Bus off state caused by transmit error
[Setting condition]
• When TEC ≥ 256
IRR7
R/W
15
0
Error Passive Interrupt Flag
0
1
[Clearing condition]
• Writing 1
Error passive state caused by transmit/receive error
[Setting condition]
• When TEC ≥ 128 or REC ≥ 128
IRR6
R/W
14
Receive Overload Warning Interrupt Flag
0
0
1
[Clearing condition]
• Writing 1
Error warning state caused by receive error
[Setting condition]
• When REC ≥ 96
Transmit Overload Warning Interrupt Flag
0
1
IRR5
R/W
13
0
[Clearing condition]
• Writing 1
Error warning state caused by transmit error
[Setting condition]
• When TEC ≥ 96
Remote Frame Request Interrupt Flag
0
1
[Clearing condition]
• Clearing of all bits in RFPR (remote request register) of mailbox for which
Remote frame received and stored in mailbox
[Setting condition]
• When remote frame reception is completed, when corresponding MBIMR = 0
Receive Message Interrupt Flag
IRR4
receive interrupt requests are enabled by MBIMR
0
1
R/W
12
0
[Clearing condition]
• Clearing of all bits in RXPR (receive complete register) of mailbox
Data frame or remote frame received and stored in mailbox
[Setting condition]
• When data frame or remote frame reception is completed, when
for which receive interrupt requests are enabled by MBIMR
corresponding MBIMR = 0
Note: * After reset or hardware standby release, the module stop bit is
Reset Interrupt Flag
0
1
Rev. 6.00 Feb 22, 2005 page 1195 of 1484
[Clearing condition]
• Writing 1
Hardware reset (HCAN module stop*, software standby)
[Setting condition]
• When reset processing is completed after a hardware reset
(HCAN module stop*, software standby)
H'F812
H'FA12
initialized to 1, and so the HCAN enters the module stop state.
IRR3
R/W
11
0
Appendix B Internal I/O Register
IRR2
10
R
0
IRR1
R
9
0
REJ09B0103-0600
IRR0
R/W
8
1
HCAN1 *
HCAN0