h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1058
h8s-2635
Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2635.pdf
(1547 pages)
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Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
23B.8.2 Exiting Watch Mode
Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or
the
(1) Exiting Watch Mode by Interrupts
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON bit
= 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits
and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed.
In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the
corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal
supporting modules, the interrupt enable register has been set to disable the reception of that
interrupt, or is masked by the CPU.
See section 23B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode
for how to set the oscillation stabilization time when making a transition from watch mode to
high-speed mode.
(2) Exiting Watch Mode by
For exiting watch mode by the
Clearing Software Standby Mode.
(3) Exiting Watch Mode by
When the
23B.8.3 Notes
(1) I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a High level is output,
the current consumption is not diminished by the amount of current to support the High level
output.
(2) Current Consumption when Waiting for Oscillation Stabilization
The current consumption increases during stabilization of oscillation.
Rev. 6.00 Feb 22, 2005 page 998 of 1484
REJ09B0103-0600
R E S
, or
S T B Y
S T B Y
pin level is driven Low, a transition is made to hardware standby mode.
pins.
R E S
S T B Y
R E S
pins
pins, see, Clearing with the
pin
R E S
pins in section 23B.6.2,
I R Q 0
to
I R Q 5
) , or signals at
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