h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1470

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Appendix B Internal I/O Register
Rev. 6.00 Feb 22, 2005 page 1410 of 1484
REJ09B0103-0600
TCSR0—Timer Control/Status Register 0
Notes: TCSR0 register differs from other registers in being more difficult to write to.
Bit
Initial value
Read/Write
For details see section 12.2.4, Notes on Register Access.
* Only 0 can be written, to clear the flag.
Note: * When interval timer interrupts are disabled and OVF is polled,
Overflow Flag
0
1
[Clearing conditions]
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR* when OVF = 1, then write 0 in OVF
[Setting condition]
• When TCNT overflows (changes from H'FF to H'00)
R/(W)*
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
OVF
read the OVF = 1 state at least twice.
7
0
Timer Mode Select
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
0
1
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from
the CPU when the TCNT overflows
Watchdog timer mode: A reset is issued when the TCNT overflows if the
RSTE bit of RSTCSR is set to 1*
WT/IT
R/W
6
0
Timer Enable
0
1
TCNT is initialized to H'00 and halted
TCNT counts
TME
R/W
5
0
Note: * An overflow period is the time interval between the
Clock Select 2 to 0
CKS2 CKS1 CKS0
0
1


4
1
start of counting up from H'00 on the TCNT and the
occurrence of a TCNT overflow.
0
1
0
1
H'FF74(W), H'FF74(R)
0
1
0
1
0
1
0
1


3
1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
CKS2
R/W
2
0
CKS1
R/W
(where φ = 20 MHz)
1
0
Overflow Period*
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
CKS0
R/W
0
0
WDT0