h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 614

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 I
Rev. 6.00 Feb 22, 2005 page 554 of 1484
REJ09B0103-0600
Bit 1
IRIC
0
1
Description
Waiting for transfer, or transfer in progress
[Clearing conditions]
Interrupt requested
[Setting conditions]
I
I
Synchronous serial format
When any other condition arises in which the TDRE or RDRF flag is set to 1
2
2
2
C Bus Interface [Option] (Only for the H8S/2638, H8S/2639, and H8S/2630)
C bus format master mode
C bus format slave mode
When 0 is written in IRIC after reading IRIC = 1
When ICDR is written or read by the DTC
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing condition; see the description of DTC operation for
details)
When a start condition is detected in the bus line state after a start condition is
issued (when the TDRE flag is set to 1 because of first frame transmission)
When a wait is inserted between the data and acknowledge bit when WAIT = 1
At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse, or at the fall of the 8th
transmit/receive clock pulse when using wait insertion)
When a slave address is received after bus arbitration is lost (when the AL flag is
set to 1)
When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
When the slave address (SVA, SVAX) matches (when the AAS and AASX flags
are set to 1)
and at the end of data transfer up to the subsequent retransmission start condition
or stop condition detection (when the TDRE or RDRF flag is set to 1)
When the general call address is detected (when FS = 0 and the ADZ flag is set to
1) and at the end of data transfer up to the subsequent retransmission start
condition or stop condition detection (when the TDRE or RDRF flag is set to 1)
When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the
ACKB bit is set to 1)
When a stop condition is detected (when the STOP or ESTP flag is set to 1)
At the end of data transfer (when the TDRE or RDRF flag is set to 1)
When a start condition is detected with serial format selected
(Initial value)