h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 489

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

12.3
12.3.1
To use the WDT as a watchdog timer, set the WT/
must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system malfunction or other
error, an internal reset is issued, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1.
If a reset caused by a signal input to the
WDT overflow, the
In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system
clock periods (516 ) (515 or 516 clock periods when the clock source is /SUB * (PSS = 1)). This
is illustrated in figure 12-4 (b).
An NMI request from the watchdog timer and an interrupt request from the NMI pin are both
treated as having the same vector. So, avoid handling an NMI request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used
with the other versions.
Operation
Watchdog Timer Operation
R E S
pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
R E S
pin occurs at the same time as a reset caused by a
I T
bit in TCSR and the TME bit to 1. Software
Rev. 6.00 Feb 22, 2005 page 429 of 1484
Section 12 Watchdog Timer
REJ09B0103-0600