h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1060

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF,
HD6432638UF, HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF,
HD6432639WF, HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF]
23B.10 Subactive Mode (U-Mask, W-Mask Version, H8S/2635 Group Only)
23B.10.1 Subactive Mode
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR (WDT1) PSS bit = 1, CPU operation shifts to
subactive mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is 1, a
transition is made to subactive mode. And if an interrupt occurs in subsleep mode, a transition is
made to subactive mode.
In subactive mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Supporting modules other than WDT0, and WDT1 are also stopped.
When operating the CPU in subactive mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
23B.10.2 Exiting Subactive Mode
Subactive mode is exited by the SLEEP instruction or the
(1) Exiting Subactive Mode by SLEEP Instruction
When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit =
0, and TCSR (WDT1) PSS bit = 1, the CPU exits subactive mode and a transition is made to
watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR
LSON bit = 1, and TCSR (WDT1) PSS bit = 1, a transition is made to subsleep mode. Finally,
when the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit = 1,
LSON bit = 0, and TCSR (WDT1) PSS bit = 1, a direct transition is made to high-speed mode
(SCK0 to SCK2 all 0).
See section 23B.11, Direct Transitions for details of direct transitions.
(2) Exiting Subactive Mode by
For exiting subactive mode by the
Clearing Software Standby Mode.
(3) Exiting Subactive Mode by
When the
Rev. 6.00 Feb 22, 2005 page 1000 of 1484
REJ09B0103-0600
S T B Y
pin level is driven Low, a transition is made to hardware standby mode.
R E S
S T B Y
R E S
Pins
pins, see, Claering with the
Pin
R E S
or
S T B Y
R E S
pins in section 23B.6.2,
pins.