h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 192

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h8s-2635

Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 5 Interrupt Controller
5.5.4
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
5.5.5
When operating by clock input, acceptance of input to an
In software standby mode, the input is accepted asynchronously. For details on the input
conditions, see section 24.5.2, Control Signal Timing.
5.5.6
When the system is operating normally under conditions conforming to the specified electrical
properties, exception processing by the on-chip interrupt controller linked to the CPU is used to
execute the NMI interrupt. When operation is not normal (runaway status) due to a software
problem or abnormal input to one of the LSI’s pins, no operations can be guaranteed, including the
NMI interrupt. In such cases it is possible to cause the LSI to return to normal program execution
by applying an external reset.
Rev. 6.00 Feb 22, 2005 page 132 of 1484
REJ09B0103-0600
L1:
Interrupts during Execution of EEPMOV Instruction
IRQ Interrupts
Notes on Use of NMI Interrupt
EEPMOV.W
MOV.W
BNE
R4,R4
L1
I R Q
pin is synchronized with the clock.

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