h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1485

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
Bit
Initial value
Read/Write
Transmit Data Register Empty
0 [Clearing conditions]
1 [Setting conditions]
Receive Data Register Full
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
0 [Clearing conditions]
1
Overrun Error
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
• When serial reception ends normally and receive data is transferred from RSR to RDR
0 [Clearing condition]
1
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Error Signal Status
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag,
• When 0 is written in ORER after reading ORER = 1 *
[Setting condition]
• When the next serial reception is completed while RDRF = 1 *
0 Normal reception, with no error signal
1 Error signal sent from receiver indicating detection of parity error
Parity Error
[Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
• When the low level of the error signal is sampled
0 [Clearing condition]
1
which retains its previous state.
• When 0 is written in PER after reading PER = 1 *
[Setting condition]
• When, in reception, the number of 1 bits in the receive data plus the parity bit *
R/(W)*
Transmit End
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
TDRE
does not match the parity setting (even or odd) specified by the O/E bit in SMR
0 Transmission is in progress
1 Transmission has ended
7
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
transmission of a 1-byte serial character when GM = 0 and BLK = 1
transmission of a 1-byte serial character when GM = 1 and BLK = 0
transmission of a 1-byte serial character when GM = 1 and BLK = 1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
1
R/(W)*
ERS
4
0
3
2
R/(W)*
Rev. 6.00 Feb 22, 2005 page 1425 of 1484
PER
3
0
H'FF7C
H'FF84
H'FF8C
TEND
Appendix B Internal I/O Register
R
2
1
4
Multiprocessor Bit
0 [Clearing condition]
1 [Setting condition]
• When data with a 0 multiprocessor
• When data with a 1 multiprocessor
Multiprocessor Bit Transfer
bit is received*
bit is received
0 Data with a 0 multi-processor
1 Data with a 1 multi-processor
Smart Card Interface 0
Smart Card Interface 1
Smart Card Interface 2
bit is transmitted
bit is transmitted
MPB
R
1
0
5
REJ09B0103-0600
MPBT
R/W
0
0