h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 578
h8s-2635
Manufacturer Part Number
h8s-2635
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2635.pdf
(1547 pages)
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Section 14 Smart Card Interface
14.3.4
Table 14-3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 14-3 Smart Card Interface Register Settings
Notes: —: Unused bit.
SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and
BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section
14.3.5, Clock.
The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer
mode.
BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of
calculating the value to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 13, Serial Communication Interface (SCI).
Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these
bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in
SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.
Rev. 6.00 Feb 22, 2005 page 518 of 1484
REJ09B0103-0600
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Register Settings
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
E
bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
Bit 6
BLK
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/
BRR4
RE
TDR4
ERS
RDR4
—
E
Bit
Bit 3
BCP1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
BCP0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
CKE1 *
TDR1
0
RDR1
—
BRR1
Bit 0
CKS0
0
BRR0
CKE0
TDR0
RDR0
SMIF
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