h8s-2635 Renesas Electronics Corporation., h8s-2635 Datasheet - Page 1451

• Manufacturer Part Number: h8s-2635
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2600 Series
• Manufacturer: Renesas Electronics Corporation.

TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
Counter Clear
Notes: 1.
0
1
CCLR2
0
1
0
1
R/W
7
0
2.
0
1
0
1
0
1
0
1
Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture *
TCNT cleared by TGRD compare match/input capture *
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation *
CCLR1
R/W
6
0
Note: Internal clock edge selection is valid when the input clock
Clock Edge
0
1

0
1
CCLR0
is φ/4 or slower. This setting is ignored if the input clock is φ/1,
or when overflow/underflow of another channel is selected.
R/W
Count at rising edge
Count at falling edge
Count at both edges
5
0
Time Prescaler
0
1
CKEG1
0
1
0
1
R/W
4
0
0
1
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Rev. 6.00 Feb 22, 2005 page 1391 of 1484
CKEG0
R/W
H'FF10
3
0
TPSC2
Appendix B Internal I/O Register
R/W
2
0
TPSC1
R/W
1
0
2
2
1
1
REJ09B0103-0600
TPSC0
R/W
0
0
TPU0